#ifndef __FPGA_REGS_MACRO__
#define __FPGA_REGS_MACRO__

#define FPGA_VERSION 0x0

#ifdef ZYNQ_MP

#else
#define AXI_CLOCK_LTE_REG 0XF8000170
#define AXI_CLOCK_LTE_200M_CLOCK 0x00100500
#endif /*ZYNQ_MP_DMA*/

#endif /*__FPGA_REGS_MACRO__*/
